Software Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for a motivated R&D engineer to help develop Cadence's Verification Acceleration and Co-Emulation environment . The engineer will be a part of cross geography team of highly experienced individuals in developing maintainable, high quality C/C++ code for a HDL language based compiler and runtime support. Responsibilities include development of HDL compiler front-end and transaction-based acceleration (TBA) compiler optimizations and RTL transformations . The candidate should be familiar with sound software engineering practices and comfortable working with large existing code base to develop new functionality and work closely with other R&D and Application engineers across geography to support TBA technologies on Cadence emulation/prototyping platforms for deployment.

Position Requirements
• BS / MS in Computer Science or equivalent required.
• At least 5 years of software and product development experience.
• Proficient in C/C++ SW development using advanced data-structures and algorithms and heuristics along with excellent and debugging skill
• Prior experience and understanding of EDA front-end tools and compiler concepts like parsing elaboration of HDL is desirable.
• Experience or understanding of System Verilog language constructs and RTL Simulation concepts with be preferred
• Hardware knowledge and background in RTL design and/or verification is highly desirable.
• Additional knowledge of shell or pearl scripting, python, and functional programming will be preferred.
• Good problem solving abilities and excellent writing and communication skills.
• Keywords – Data Structures, Algorithms C/C++, System Verilog, RTL Simulation, Compilers, UVM, TLM, RTL modeling, emulation.

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