Design Verification Engineer

Veloce Transactors (Accelerated Verification IPs) Veloce Transactor Group is part of Siemens Emulation Division R&D located in Noida. Group is responsible for developing transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile etc. At present Veloce Transactor Library supports more than 25 protocol solution and expanding further.

Position: Design and Verification Engineer

Work Experience: min 2 years

(BE/BTech/ME/MTech/MS) From any of the premier engineering institutes.

Primary Technical skills:

1. Hands on experience on the protocol e.g. PCIe, USB, Ethernet, AMBA in Design or Verification.

2. Verilog / System Verilog / System C

3. RTL in developed for FPGAs/ASICs/IPs

Or
• Good understanding of IP Verification Methodologies, Verification procedures and practices are plus.
• Individual will be responsible for developing transactor (xVIP) solutions for Ethernet/5g Protocols/CXL or PCIe based interconnect technology.
• Primary responsibilities include understanding standard specifications, develop architecture and micro-arch for the design and writing a RTL design using Verilog/System Verilog, create verification test plans and environments, testcase development, VIP usage, and the ability to debug of defects found through verification processes.
• Individual would need to engage with customers for Deployment and R&D assistance.
• Exposure of object-oriented programming using languages such as C++ is advantage
• Experience in scripting languages such as Perl, Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc