Agasthya App Labs Senior Verification Design Engineer UVM ...
Published date: 2026/11/07
- Location: Ahmedabad, Gujarat, India
Minimum 6 years experience in ASICFPGA verification, including verification of complex ASICs at chiplevel Expertise in SystemVerilogUVM Knowledge of C andor Python preferred Networking protocol (i.e. Ethernet, OTN) andor FEC experience is a must Basic knowledge of SerDes and ADCDAC a plus Expertise in independently building SVUVM test benches Expertise in developing test cases and test plans Functional coverage, code coverage closure experience a must Gate sims and debugging. Experience in lab validation and bring up activities is a plus
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